The present invention relates generally to current mode logic (CML) circuits.
CML (current mode logic) is widely used for high-speed bipolar logic circuitry because of its low power consumption and relatively low supply voltage compared to emitter coupled logic (ECL). CML also tends to provide a good-quality output signal to the outside of a chip in view of its stable electrical output transfer function.
In this vein, it should be noted that CML and ECL circuits generally represent some of the fastest logic circuits presently in existence as they are composed of bipolar transistors, which have higher transconductance (or, essentially, higher driving capability, so as to drive the circuit load easily and fast). However, CML and ECL logic circuits require static power consumption, meaning that they always draw current from the available power in order to retain to the desired logic function, such that these circuits usually consume high power. Also, bipolar transistors tend to require a significant amount of area. Accordingly, CML and ECL circuits overall are recognized as being high-power circuits that occupy a large amount of area.
CML and ECL circuits, since they are significantly faster than CMOS logic, find use as output drivers in high-speed circuits. However, when CML""s are used for output drivers, the output signal levels generally have to be adjusted to communicate with the receiver. Also, in many instances, the common mode of the output must go into a high-impedance state for xe2x80x9ctestabilityxe2x80x9d features of the circuit. In this vein, it is recognized that the level integration of such circuits is very high, but the number of input and output terminals of the circuit that one can normally probe is limited to only a few hundreds at most. Since circuits generally need to be verified in some manner, they are often verified through the limited number of input and output terminals; otherwise it may not be know which chips do or do not actually function properly. To adequately test the circuit overall, however, including components thereof that are internal and thus cannot be directly probed, the circuit has to be configured for testability. For example, one may apply a unknown sequence or a set of signals to the I/O pins, operate the circuit, then read the results. At that point, the functionality of the entire circuit can be statistically verified. In order to accomplish this, however, an output driver may have to be bi-directional so that it can take an external signal and pass it to the internal circuit. For this reason, the output driver may need to go into a high-impedance state so that it can operate as a receiver.
A need has been recognized in connection with adequately attending to both of these requirements.
In accordance with at least one presently preferred embodiment of the present invention, a high impedance state is implemented at the CML output for a bi-directional buffer. The output common mode voltage can be adjusted at the same time, which is particularly useful for a CML off-chip driver.
Accordingly, as a consequence of adopting the arrangements contemplated herein, high impedance output is attained with the current mode logic (CML) circuit along with control of the output common mode voltage. This is of particular use to CML-type output driver circuits to achieving a required output common mode voltage.
In one aspect, the present invention provides an arrangement for stabilizing the output common mode voltage of an output stage.
For a better understanding of the present invention, together with other and further features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, and the scope of the invention will be pointed out in the appended claims.